The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices requires minimal design features less than 0.30.mu., e.g., 0.25.mu. and under, increased transistor and circuit speeds, high reliability and increase manufacturing throughput for competitiveness. The reduction of design features to 0.25.mu. and under generates acute problems challenging the limitations of conventional semiconductor manufacturing technology, particularly for increased manufacturing throughput and cost reduction.
Conventional semiconductor manufacturing methodology comprises numerous processing steps, including photolithographically printing and transferring a plurality of integrated circuit patterns on a wafer or die surface on a plurality of metal layers spaced apart by dielectric interlayers and connected by vias. The proper functioning of the final semiconductor device depends upon precise alignment of the various circuit patterns and layers formed thereon. Misalignment of a single pattern or layer can prove catastrophic to circuit functionality.
Conventional semiconductor manufacturing methodology comprises photolithographically printing circuit patterns in device forming areas on layers utilizing photoresist masks having openings therein which define the various patterns. A typical photolithographic technique is commonly referred to as a step-and-repeat pattern transfer system ("stepper") involving imaging of several exposures of portions of the wafer to cover an entire wafer surface. During photolithographic printing, alignment is ensured by reference to alignment marks formed on the wafer surface outside the device forming area on which the circuits are printed.
To achieve the requisite high degree of precision required for aligning the various layers and printed circuits, alignment marks are conventionally etched in the wafer surface so that, in each photolithographic step, the mask is properly aligned according to the alignment marks before exposing the wafer. Typically, four alignment marks are provided, circumferentially positioned about the periphery of the wafer, although alignment can be achieved with fewer or greater than four alignment marks and can be positioned at any convenient location.
Alignment marks must be sharply defined and extend to only a shallow depth into the wafer surface to obtain the requisite alignment signal strength for proper recognition by the stepper. A typical depth of an alignment mark required by conventional steppers manufactured by ASM Lithography is 1,200.ANG.. Alignment marks for steppers marketed by other manufacturers may require slightly different depths. Alignment is particularly critical in manufacturing semiconductor devices having submicron design features of less than 0.30.ANG., such as 0.25.ANG. and under.
The formation of sharply defined alignment marks disadvantageously requires several processing steps typically performed before formation of active components in the device forming area. Conventional methodology for forming alignment marks comprises cleaning a substrate surface, growing or depositing a silicon oxide layer thereon, depositing a photoresist material on the silicon oxide layer and subsequently patterning the photoresist material by a photolithographic technique to form a mask having an opening for an alignment mark. The alignment mark is then transferred to the substrate by anisotropic etching, and is conventionally referred to as the zero layer etch. Typical anisotropic etching comprises reactive ion etching (RIE) to form substantially orthogonal sidewalls substantially perpendicular to the substrate plane. The photoresist mask is then removed leaving an alignment mark having a depth of about 1,200.ANG. in the substrate. The oxide layer is then removed leaving the alignment mark for use in photolithographic processing to align subsequently formed photoresist masks in forming various elements, integrated circuitry and interconnect patterns.
Subsequent to forming the alignment marks, conventional practices comprise isolating an active region, as by trench isolation. A trench isolation methodology typically comprises forming a pad oxide layer on a substrate surface and a nitride layer thereon. A photoresist mask is formed on the nitride layer and anisotropic etching is conducted to form a trench in the substrate. Thermal oxidation is then performed to grow an oxide liner on the trench walls to control the silicon-silicon dioxide interface quality. The trench is then refilled with an insulating material, such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP).
In copending application Ser. No. 08/789,255 filed on Jan. 28, 1997, methodology is disclosed for providing alignment marks free from nitride residue by etching the alignment marks to an ultimate depth of about 1,200.ANG. subsequent to deposition of a nitride layer and before shallow trench isolation formation, to ensure precise alignment of a mask during subsequent processing of the semiconductor die wafer. Such methodology constitutes an improvement over conventional practices; however, the formation of an alignment mark requires separate manipulative steps.
There exists a need for semiconductor manufacturing methodology with a reduced number of processing steps, thereby increasing production throughput and reducing costs. There exists a particular need for improving the efficiency of semiconductor manufacturing technology in forming high density devices having minimal dimensions.